Making of a System-on-Chip

New generation handheld devices such as, cellphones, PMPs, etc. are getting thinner, more powerful and sophisticated. Here we look at all it requires to make a single integrated circuit called System-on-Chip

Friday, October 03, 2008

Today's mobile phones have more processing power than typical desktop computers of the last millennium. Even the Portable Media Players (PMPs) have more sophisticated processors than the revolutionary Pentium processor launched 15 years back. On top of that, mobile phones, PMPs and other handheld devices are getting smaller and thinner with increasing battery life.

So, what makes these new generation handheld devices tick? Ticking at 200MHz or more, these devices are powered by a small silicon chip -the size of about 10mm x 10mm, which contains almost all components of a powerful computer including processor core, memory controller, interrupt controller, timer, multimedia co-processors or digital signal processor (DSP) etc. This silicon chip, along with the software running on it, is called a System-on-Chip or SoC.

What is a SoC?
System-on-chip is an integration of almost all components of a computer into a single integrated circuit (chip). The SoC consists of both the hardware (HW) components of the computer as well as the software (SW) that controls the microprocessor and peripherals.

The block diagram of a typical SoC is shown in Figure 1, and Figure 2 shows a generic software stack for the same.

SoC architectures
The generic SoC architecture consists of the processor, system bus, timers, memory, interrupt controller and power management circuits. The other peripherals such as LCD controllers, USB interface; Flash memory interfaces etc. are optional and depend on the target application of the SoC.

SoCs for multimedia platforms – such as mobile phones or PMPs, require a large amount of audio and video processing. There are two schools of thoughts in the industry to achieve better multimedia experience for the user:Dedicated DSP and Dedicated multimedia blocks.

Some SoC designers use a dedicated DSP along with the main processor. The Audio and Video processing is shared between the main processor and the DSP. E.g. the main processor may be decoding audio, while the video is decoded on the DSP. This approach allows for more generic application of the SoC and also allows scalability in the future as new codecs are released in the market. But this approach may increase the size of the chip and also increase the power utilization.

Other designers prefer using dedicated blocks for processing popular Audio and Video encoding formats. E.g. there can be dedicated hardware blocks for MP3 decoding, H.264 decoding, MPEG4 encoding etc. This approach may be more optimized in terms of size and power, but application and scalability may be limited.

The approach used in a particular SoC will usually depend on the application, market requirements and other constraints like cost and power.

SoC design flow
The design of any SoC starts with the requirement specification and architecture exploration. The design team identifies all the processing blocks along with their interconnections. A lot of time is devoted to the hardware and software partitioning. This is essential for optimization of the performance of the SoC as well as the costs involved. E.g. if the SoC requires processing of 3D Graphics - the options for implementing the required processing logic or algorithm are as follows:

• Use a collection of interconnected logic gates (AND/NAND/NOR etc.) as a HW block
• Implementation as a software library running on the main processor
  

Once the partitioning is finalized, the HW team starts working on the implementation of the architecture platform. It consists of the main processor core and the system buses. The main processor core is usually available as a component from core vendors such as ARM or Tensilica. The system bus can be either an industry standard architecture such as AMBA, or can be designed specifically be the HW team. Next is design and implementation of HW blocks – called HW IPs (intellectual property) using a hardware description language such as VHDL or Verilog. Examples of HW blocks can be – USB controller, memory controller, LCD controller etc. depending on the SoC requirements. Not all HW blocks are designed and implemented by the HW team; some HW blocks are purchased or licensed from 3rd parties who sell these as components. These may be commonly used blocks such as serial bus controllers, memory controller, interrupt controllers or can be very specialized blocks such as multimedia codecs, 3D accelerators etc.

Next comes the integration of the HW blocks with the architecture platform. This involves creating interconnection or bridges for the processor to communicate and control each HW block. The whole system is then tested using various verification techniques such as functional simulation.

The HW system is essentially a collection of logic gates and their interconnections. To further verify the functionality of the HW system, the HW team uses a field-programmable gate array (FPGA). An FPGA is a silicon chip which consists of programmable logic (gates) and programmable interconnects. The entire HW system can be realized using one or more FPGAs. The FPGAs are set on a PCB which has similar external interfaces as the final SoC.

Since the FPGAs are reprogrammable, the HW team can test and modify their implementation to eliminate bugs. The FPGA board with the HW system is also used by the software team to co-simulate the entire system (SW+HW) and eliminate bugs in both HW blocks and software programs.

The HW system implementation is done using Software tools on development workstations running Windows or Linux. These software tools are called the Electronic Design Automation (EDA) tools available from companies such as Cadence, Synopsis and Mentor Graphics.

While the HW team is busy creating the HW System, the software team can start developing the SW system. They create an environment on a development PC (running Windows or Linux) simulating the SoC. There are many tools available to create such environments. Mostly the tools are specific to the Operating System chosen to run on the final SoC. E.g. the Windows CE tools from Microsoft provide emulated execution environments on the PC itself for developing software. Next comes the design and implemetation of components such as multimedia codecs, application software etc. – these components are tested on the simulation environment on the PC.

Once the FPGA board is ready with the HW system, the SW team can start porting the operating system on to the FPGA board. The device driver development is also done at this stage.

Once the HW and SW system on the FPGA board is stabilized and bug fixing is complete, the HW team proceeds with the physical design of the SoC. This involves developing the layout of the gates for the final realization on Silicon.

This is a complex process usually termed as 'backend process'. The HW design is then sent to the Semiconductor Fabrication Plant (FAB) for making of the final chip (ICs) on silicon. This process is called 'tape-out'. The first sets of ICs are called the engineering sample and are made available to the HW and SW team for verification.

The verification process involves finding bugs in the IC and finding workarounds to fix them – since the HW cannot be modified easily, most of the bugs are fixed using software patches. If there are too many bugs, or some bugs affect the functionality of the SoC, then the HW design is fixed and a second tape-out may be required. This is termed as a re-spin and can be expensive.

When the engineering samples are found to be good enough to hit the market, a mass production is ordered to the FAB and the ICs are shipped to the customer with all associated software. The customers are often the original equipment manufacturers (OEM) who make the final product using the SoC and other components.

Intel, Samsung, ST Microelectronics, Texas Instruments and Qualcomm are some Semiconductor companies, which make the SoCs and ship them to OEMs such as Nokia, Apple, HP, HTC and Motorola. E.g. the new HTC Touch Diamond Smartphone is powered by a Qualcomm SoC (MSM7201A) which has an ARM 1136 CPU Core running at 528MHz.

SoC design considerations
The focus of all SoCs designers is to deliver maximum performance at the lowest cost and lowest power consumption. Many factors contribute to SoCs characteristics:

Process Technology – The SoCs are manufactured using a Silicon fabrication technology called Complementary metal–oxide–semiconductor (CMOS). Logic gates are created on a Silicon wafer using the CMOS process technology. The gates are then interconnected to realize the HW system of the SoC. The CMOS process technology has been evolving over the years with the size of the gate reducing considerably. Smaller size of each gate means a closer packing of the gates on the silicon chip. The packing of gates which is roughly the distance between them is measured in nanometres (nm). A smaller size indicates a more advance process. The commonly used process these days ranges from 180 nm to 90 nm. Some FABs also have capability of 65 nm and 45 nm.
The advancement in the process technology has been a key contributor of the evolution of the SoC. More and more gates, which in turn mean more and more functionality, can be put in a single SoC thus reducing the number of ICs inside a product. This has led to thinner, smaller and more power efficient handheld products.

The CMOS process technology is also optimized for either higher speed or lower power consumption. The SoC designers can select the process based on the requirements of the target SoC and its applications.

Die Size – This is the physical surface area of the silicon used to make a single IC. Die size is measured in mm2. The importance of die size is that it translated directly to cost. Smaller die size of a chip means that more of them can be made from a single wafer, thus reducing cost. Die size depends on the number of gates required to realize a particular HW System for a SoC.

SoC designers try to optimize the die size to reduce cost. They try to optimize the algorithms used to realize a particular functionality and also optimize the gates required to implement the algorithm. Another target is to reuse a particular HW block for multiple functionalities to reduce die size. SoC designs frequently require performance vs. die size decisions.

Power – Most handheld devices run on battery power and power consumption of a SoC becomes a prime consideration for OEMs as this is an important buying consideration for users.

Power management – the process of reducing power consumption – involves controlling standby power, reducing leakage currents, switching off HW blocks which are not in use at the moment, slowing down the main processor during low usage periods etc.

E.g. in a mobile phone, the USB controller can be switched off when the phone is not connected to a PC, the LCD can be switched off after some time of inactivity. Also, the main processor clock can be slowed down to bare minimum when the phone is not in use.

Power management in SoCs for handheld devices is one of the most complex tasks faced by the SoC designers.

Hardware Software Partitioning – One of the initial discussions during the design of a SoC is on the question of what goes into HW and what is implemented in SW. The factors involved are
1. HW is faster than SW
2. A large amount of parallel processing can be done in HW
3. There is limited flexibility in HW, functionality cannot be modified
4. Any bug found in HW may require an expensive re-spin
Since point 1, 2, contradict with 3, 4, the decisions of partitioning are complex and require a lot of deliberation.
Operating System – The design of the SoC also depends on the type of operating system that will be running on the processor. This is usually dictated by the application of the SoC and the choice of the target customers.

If the SoC is targeted to run real time operating systems such as VxWorks, uITRON etc. then some blocks such as Memory Management Unit (MMU) may not be required. On the other hand, if the target OS is Windows CE or Embedded Linux, then MMU becomes essential along with certain amount of Cache memory.

The above factors are a subset of all the factors that affect the design of a SoC. See the links for further reading at the end of the article.

Future trends
The ever increasing requirement on the functionality of handheld devices is pushing the SoC designers to make more powerful, power efficient and cost effective SoCs with more and more functionality going into a single chip which is getting smaller and thinner.

Latest SoCs feature CPU cores running at 500 MHz or more, peripherals include LCD and Touch panel interface, camera interface, USB host/device, WLAN, Bluetooth, TV Out, Flash memory controllers for Compact Flash, Memory Stick, SD Card etc., complex HW blocks such as multi-format codecs, 3D accelerators, GPS Baseband, 3G Modems, and DSP cores.

Sudipto Chanda

Page(s)   1